1. Field of the Invention
The present invention relates to a signal level conversion circuit, and more particularly, it relates to a signal level conversion circuit which converts a level of a signal from one power potential to the other power potential in a case where signals are transmitted/received between different power potentials.
2. Description of the Related Art
In general, in a system including a central processing unit (CPU), there exist a large number of bus (signal) lines via which data is exchanged between the CPU and various peripheral devices, and these various peripheral devices are connected to the bus as if they were hanging. With improvement of a processing capacity of the CPU, power consumption increases, and hence, processes are finely divided and a power voltage is lowered to suppress the increase of the power consumption. In the peripheral devices connected to the CPU, however, there has been a tendency that the lowering of the power voltage does not easily advance in many cases.
This tendency is often seen in battery drive apparatuses driven by batteries, and examples of the battery drive apparatus include applications such as cellular phones and personal digital assistants (PDA). In these applications, there has been a demand for a reduced power consumption in order to lengthen a use time, especially a demand for a low power consumption with respect to the CPU. However, in these peripheral apparatuses connected to a bus, it has been difficult to change the power voltage because of necessity of maintaining compatibility in the present situations. Therefore, signals having different power levels are supplied to the bus. However, when the signals having different power levels are supplied to the bus, current consumption of the system is increased, devices are broken, or malfunctions of the devices are caused. Therefore, an integrated circuit device for converting the power level of the signal is required. FIG. 22 is a block diagram showing a schematic constitution of a general signal level conversion circuit driven at different power levels. The block diagram shows a case where VccA<VccB is set.
A system 1 of a bidirectional level shifter shown in FIG. 22 includes a VccA system circuit 2 which operates at a power level A, and a VccB system circuit 3 which operates at a power level B. When a signal flows in a direction of an arrow 4 to a terminal B1 from a terminal A1, the system includes a first input buffer circuit 5, a level shifter circuit 6 which converts the level of a power supply, a first (A to B) logic circuit 7, and a first output buffer circuit 8. It is to be noted that in the block diagram of FIG. 22, the first logic circuit 7 is interposed between the level shifter circuit 6 and the first output buffer circuit 8 in the flow of the signal in the arrow 4 direction, but the first logic circuit 7 may be disposed in any signal path extending to terminal B from terminal A. For example, as shown in a dot-line block of FIG. 22, the first logic circuit may also be interposed between the first input buffer circuit 5 and the level shifter circuit 6 of the VccA system circuit 2.
Either of the VccA system circuit 2 and the VccB system circuit 3 to be operated is controlled by a control circuit 9. In the control circuit 9, an operation direction is switched to the direction of the arrow 4 or an arrow 10 by signals input from an input terminal DIR of a direction switching signal and an input terminal *OE of an operation signal. When the signal flows in the direction of the arrow 10 to the terminal A1 from the terminal B1, the system includes a second input buffer circuit 11, a second (B to A) logic circuit 12, and a second output buffer circuit 13. It is to be noted that “*” in the operation signal *OE means that the potential of the signal is reversed in this specification.
The system shown in FIG. 22 shows a case where the power level has a relation of VccA<VccB as described above. For example, considering that the terminal A1 is an input and the terminal B1 is an output, the signal which has entered the terminal A1 is inputted into the level shifter circuit 6 through the first input buffer circuit 5. After the level is converted to VccB from VccA in the level shifter circuit 6, and a predetermined logic operation is performed in the first logic circuit 7, a signal having a VccB level is outputted to the terminal B1 from the first output buffer circuit 8. The level shifter circuit 6 is inserted to securely turn off a P-channel transistor of the first output buffer circuit. When “VccA<VccB”, and when the level shifter circuit 6 is not disposed, a voltage Vgs (voltage from gate to source) between gate and source of the P-channel transistor is not 0 V, the P-channel transistor does not turn off, and a through current is passed.
When the terminal B1 is an input and the terminal A1 is an output, the level shifter circuit does not have to be interposed between the second input buffer circuit 11 and the second (B to A) logic circuit 12, and the signal input from the terminal B1 is outputted as a signal of a VccA level to the terminal A1 via the second input buffer circuit 11, second (B to A) logic circuit 12, and second output buffer circuit 13.
A concrete constitution of a conventional system shown in FIG. 22 will be described with reference to a circuit diagram of FIG. 23. In FIG. 23, the terminal *OE having the VccB level brings both the terminals A and B into a high impedance (HZ) state. When the terminal *OE has a ground (GND) level, the terminal A, B is set to be the input or the output. The terminal DIR having the VccB level uses the terminal A as the input, and the terminal B as the output. When the terminal DIR has a ground (GND) level, the terminal B is set to the input, and the terminal A is set to the output.
Now an operation in an example in which the terminal A is the input and the terminal B is the output (i.e., *OE=GND, DIR=VccB) will be described. When a signal having the VccA level is inputted into the terminal A, a node α has a GND level, N2, P1 of the level shifter circuit 6 turn on, N1, P2 turn off, the VccB level is outputted to a node β, and the level can be converted to VccB from VccA.
However, since the number of devices forming the circuit is large in the constitution of the prior-art level shifter circuit in the bidirectional system shown in FIG. 23, there has been a disadvantage that a chip size increases. Moreover, since the constitution includes six stages in total including the first input buffer circuit 5 (first stage), level shifter circuit 6 (second, third stages), first (A, B) logic circuit 7 (fourth stage), and first output buffer circuit 8 (fifth, sixth stages), a propagation time of the signal is delayed, and there is also a problem that delay is generated in the signal propagation.
It is to be noted that as a bus system operating at different power levels, not only the bidirectional system shown in FIGS. 22, 23 but also a one-way system shown in FIG. 24 are used. A second prior art which is the one-way system will be described with reference to FIG. 24.
A basic constitution of the one-way system shown in FIG. 24 corresponds to that of the bidirectional system of FIG. 23 except that the terminal DIR for inputting the direction switching signal to control a processing direction of the signal is not disposed. Therefore, the same constituting elements are denoted with the same reference numerals, and redundant description is omitted. It is to be noted that even in the one-way system shown in FIG. 24, the power voltage has a relation of VccA<VccB, and the operation of the one-way system is the same as that in a case where the signal is processed to the terminal B from the terminal A in the bidirectional system. Since the one-way system does not include the terminal DIR, there is not any complexity of the control as in the bidirectional system. However, the circuit constitution is still complicated, and there is a problem that the chip size increases in the same manner as in the bidirectional system. Furthermore, the problem that the delay is generated in the signal propagation time also occurs in the same manner as in the bidirectional system.
As described above, according to the conventional signal level conversion circuit, the level shifter circuit includes a two-stage constitution, whether the signal processing system is one-way or bidirectional. Therefore, the circuit constitution becomes complicated, and there has been a problem that the chip size increases. The delay is generated in the signal propagated through the signal processing system in which the level shifter circuit including a large number of stages is disposed. There is also a problem that the signal propagation in a signal processing direction from a terminal side on which the signal level is low to that on which the signal level is high is delayed. According to the present invention, there is provided a signal level conversion circuit in which the number of stages of a signal processing system including a level shifter circuit is decreased to simplify a circuit constitution, so that a chip size can be decreased, and a delay in signal propagation can be reduced.